Silicon Labs /Series1 /MGM13 /MGM13S12F512GN /VDAC0 /IEN

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Interpret as IEN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH0CD)CH0CD 0 (CH1CD)CH1CD 0 (CH0OF)CH0OF 0 (CH1OF)CH1OF 0 (CH0UF)CH0UF 0 (CH1UF)CH1UF 0 (CH0BL)CH0BL 0 (CH1BL)CH1BL 0 (EM23ERR)EM23ERR 0 (OPA0APORTCONFLICT)OPA0APORTCONFLICT 0 (OPA1APORTCONFLICT)OPA1APORTCONFLICT 0 (OPA2APORTCONFLICT)OPA2APORTCONFLICT 0 (OPA0PRSTIMEDERR)OPA0PRSTIMEDERR 0 (OPA1PRSTIMEDERR)OPA1PRSTIMEDERR 0 (OPA2PRSTIMEDERR)OPA2PRSTIMEDERR 0 (OPA0OUTVALID)OPA0OUTVALID 0 (OPA1OUTVALID)OPA1OUTVALID 0 (OPA2OUTVALID)OPA2OUTVALID

Description

Interrupt Enable Register

Fields

CH0CD

CH0CD Interrupt Enable

CH1CD

CH1CD Interrupt Enable

CH0OF

CH0OF Interrupt Enable

CH1OF

CH1OF Interrupt Enable

CH0UF

CH0UF Interrupt Enable

CH1UF

CH1UF Interrupt Enable

CH0BL

CH0BL Interrupt Enable

CH1BL

CH1BL Interrupt Enable

EM23ERR

EM23ERR Interrupt Enable

OPA0APORTCONFLICT

OPA0APORTCONFLICT Interrupt Enable

OPA1APORTCONFLICT

OPA1APORTCONFLICT Interrupt Enable

OPA2APORTCONFLICT

OPA2APORTCONFLICT Interrupt Enable

OPA0PRSTIMEDERR

OPA0PRSTIMEDERR Interrupt Enable

OPA1PRSTIMEDERR

OPA1PRSTIMEDERR Interrupt Enable

OPA2PRSTIMEDERR

OPA2PRSTIMEDERR Interrupt Enable

OPA0OUTVALID

OPA0OUTVALID Interrupt Enable

OPA1OUTVALID

OPA1OUTVALID Interrupt Enable

OPA2OUTVALID

OPA2OUTVALID Interrupt Enable

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